FIGS. 9 and 10(a)-10(h) are views for describing a two-stage recess structure FET described in Proceedings of SOTAPOCS XIII, page 79, where FIG. 9 is a cross-sectional view showing a structure of a gate electrode part of the FET and FIGS. 10(a)-10(h) are cross-sectional views showing major process steps in the production of the gate.
In the figures, reference numeral 200 designates an FET having a two-stage recess structure. An n type GaAs layer 22 is disposed on a GaAs substrate 20 and a GaAs buffer layer 21, and a gate electrode 30 is disposed at the center of a gate recess 201 in a prescribed region on the n type GaAs layer 22. The gate recess 201 has a two-stage recess structure having a first recess bottom surface 201a at the central portion of the recess in contact with the gate electrode 30 and second recess bottom surfaces 201b at both sides of the first recess bottom surface 201a. The second recess bottom surfaces 201b are positioned at a depth between the first recess bottom surface 201a and the upper surface of the n type GaAs layer 22 and are not in contact with the gate electrode 30.
High dopant concentration n type GaAs layers 23 are disposed on the upper surface of the n type GaAs layer 22 at both sides of the gate recess 201 and source and drain electrodes 25a and 25b are disposed on these n type GaAs layers 23. The upper surfaces of the n type GaAs layers 23 and the source and drain electrodes 25a and 25b are covered with SiO.sub.2 films 24, and a passivation film 31 comprising an SiN film is disposed on the entire surfaces of the SiO.sub.2 films 24, the n type GaAs layer 22, and the gate electrode 30.
In addition, a mask layer 25 comprising a polyimide film is provided for evaporation and lift-off of a gate electrode material. Ni layers 29 are provided for patterning the mask layer 25. An Au layer 26 is provided as a feeding layer while forming the Ni layers 29 by selective plating. A photoresist mask 28 is provided to perform the Ni plating selectively. A Ti thin film 27 disposed between the Au layer 26 and the photoresist mask 28 is provided to enhance adhesion between the photoresist mask 28 and the Au layer 26 and to reduce reflection during exposure of a photoresist film 28a.
In the production method, first of all, the GaAs buffer layer 21, the n type GaAs layer 22, and the high concentration n type GaAs layer 23 are successively formed on the GaAs substrate 20 by epitaxial growth, the SiO.sub.2 film 24 and the polyimide film 25 are successively deposited on the high dopant concentration n type GaAs layer 23, the Au thin film 26 and the Ti thin film 27 are formed on the polyimide film 25, and the photoresist film 28a is plated on the entire surface, as shown in FIG. 10(a). Here, the source and the drain electrodes are not illustrated, but they are already present at a prescribed region on the high dopant concentration n type GaAs layer 23.
Subsequently, the photoresist film 28a is patterned to form the photoresist mask 28 and, thereafter, a part of the Ti layer 27 exposed by this patterning is removed by RIE (reactive ion etching) using CBrF.sub.3 gas, and the Ni layers 29 are selectively plated on the exposed part of the Au layer 26, as shown in FIG. 10(b).
Next, the photoresist mask 28 and the Ti layer 27 are removed as shown in FIG. 10(c) and, thereafter, a part of the polyimide layer 25 exposed to the aperture of the Ni gilding layer 29 is selectively etched by RIE using O.sub.2, thereby forming a polyimide layer aperture 25a, and, further, a part of the SiO.sub.2 film 24 exposed to the polyimide layer aperture 25a is selectively etched by RIE using CF.sub.4 gas, thereby forming an SiO.sub.2 film aperture 24a, as shown in FIG. 10(d).
A part of the high concentration n type GaAs layer 23 exposed to the SiO.sub.2 film aperture 24a is etched for a recess having a depth of approximately 500 .ANG. (50 nm), thereby forming a recess 202 as shown in FIG. 10(e) and, thereafter, the SiO.sub.2 film 24, the high dopant concentration n type GaAs layer 23, and the n type GaAs layer 22 are etched to produce an undercut of about 0.6 .mu.m, thereby forming the gate recess 201 as shown in FIG. 10(f). In this etching step, because the n type GaAs layer 23 has been previously etched as shown in FIG. 10(e), a gate recess 201 having a two-stage configuration with the first bottom surface 201a in contact with the gate electrode and positioned at the center part in the recess and the second bottom surfaces 201b not in contact with the gate electrode and positioned at a little higher position than the first bottom surface 201a at both sides of the first bottom surface is produced.
Thereafter, Ti, Pt, and Au as gate electrode materials 30a are successively evaporated as shown in FIG. 10(g), the gate electrode materials 30a are lifted-off by removing the polyimide layer 25, thereby forming the gate electrode 30, and, finally, the SiN film 31 is deposited on the entire surface as a passivation film, thereby providing the FET 200 with the two-stage recess structure as shown in FIG. 10(h).
The gate recess structure and the characteristics of the FET are related as described below in comparing a two-stage recess structure to a one-stage recess structure.
FIGS. 11(a) to 11(c) are diagrams schematically showing a two-stage recess structure, a one-stage recess structure, and a one-stage recess structure having a wide recess width in FETs, respectively. In the figures, a two-stage recess structure gate recess 310 is provided in an n type semiconductor layer 322, and has a first-stage recess 311 having an aperture width W11 with a bottom surface 311a on which a gate electrode 350 is disposed and a second stage-recess 312 having an aperture width W12 having a bottom surface 312a positioned at a higher position than the bottom surface 311a of the first-stage recess 311. Reference numerals 320 and 330 designate one-stage gate recess structures having aperture widths of W2 and W3 (&gt;W2) and having recess bottom surfaces 320a and 330a, respectively. Reference numeral 322a designates a surface depletion layer of the n type semiconductor layer 322 having a thickness Dsd. Reference numeral 322b designates a gate depletion layer that extends farther toward the drain side along the lower surface of the surface depletion layer 322a with an increase in the gate voltage.
Because the bottom surfaces 312a of the second-stage recess 312 are positioned at both sides of the bottom surface 311a of the first-stage recess 311 on which the gate electrode 350 is disposed in the gate recess 310 as shown in FIG. 11(a), the active layer thickness Da2 at the side of the gate electrode is thicker than the active layer thickness Da at the side of the gate electrode of the gate recess 320 in the one-stage recess structure FET shown in FIG. 11(b). Therefore, the two-stage recess structure FET shown in FIG. 11(a) is unlikely to be subject to channel confinement in which the path of current flowing between the source and the drain is narrowed due to the surface depletion layer 322a at the upper surface of the n type semiconductor layer 322 as compared with the one-stage recess structure FET shown in FIG. 11(b). As a result, preferable input and output characteristics of the FET are obtained with the two-stage recess structure.
Furthermore, it is known that in the two-stage recess structure FET, even when the thickness Da1 of the n type semiconductor layer 322 at a part directly below the gate electrode is the same as the thickness Da in the one-stage recess structure FET, the active layer thickness at the source side part in the gate recess is larger than that in the one-stage recess structure FET as described above so that the source resistance is lowered as compared with the one-stage recess structure FET, improving FET performance.
Generally, the following factors are important for further improvement of high frequency and output characteristics of FETs: (1) suppression of channel confinement, (2) reduction of source resistance, and (3) improvement of gate drain breakdown voltage. The two-stage recess structure is effective in realizing (1) and (2) as described above.
It is known that the gate drain breakdown voltage greatly depends on the ratio of the thickness of the active layer at the side of a gate electrode to the thickness of a surface depletion layer at the same part and that the gate drain breakdown voltage increases with an increase in the ratio, as described in IEEE Trans. Electron Devices, Volume ED-276, 1013, 1980. Accordingly, in the two-stage recess structure, because the ratio of the surface depletion layer thickness to the active layer thickness at the side of the gate electrode (Dsd/Da2) is smaller than that ratio in the one-stage recess structure (Dsd/Da), the gate drain breakdown voltage is decreased, resulting in a problem.
More particularly, in FETs, when the voltage applied to the gate electrode 350 is increased, the gate depletion layer 322b does not extend in the thickness direction of the active layer (hereinafter referred to as vertical direction) but extends in the transverse direction. The gate drain breakdown voltage depends on the distance of the gate depletion layer 322b extending in the transverse direction, and the gate drain breakdown voltage is large when this distance is large. To be more specific, because the thickness Da2 of the active layer at the side of the gate electrode in the two-stage recess structure shown in FIG. 11(a) is larger than the thickness Da in the one-stage recess structure shown in FIG. 11(b), the distance of the gate depletion layer 322b extending in the vertical direction, i.e., a value Dgd1 which is obtained by subtracting the surface depletion layer thickness Dsd from the thickness Da2 of the active layer at the side of the gate electrode, is larger than the value Dgd (=Da-Dsd) in the one-stage recess structure shown in FIG. 11(b). Therefore, the gate depletion layer 322b is unlikely to extend in the transverse direction in the two-stage recess structure as compared with the one-stage recess structure, resulting in a low gate drain breakdown voltage.
Besides, it is generally known that the gate drain breakdown voltage is improved with an increase in recess width which is obvious from the above description. In a recess structure having a large recess width, however, when the gate drain breakdown voltage is increased, the source resistance is increased because of an increase in the recess width at the source electrode side, resulting in a problem.
More particularly, in the recess structure having the large recess width W3 as shown in FIG. 11(c), because the gate depletion layer 322b does not extend in the vertical direction and the distance Lcd3 of the gate depletion layer extending toward the drain side is longer than Lcd2 of FIG. 11(b), the gate drain breakdown voltage is high. On the other hand, because the recess width W3s at the source electrode side is larger than the W2s width of FIG. 11(b), an increase in the source resistance is induced.
Japanese Published Patent Applications 60-28275 and 4-39941 describe FETs having a gate recess structure in which a gate electrode is disposed on a concave part of an upper surface of a semiconductor substrate and has an intermediate bottom surface only at the source side of the side surface of the concave part. The intermediate bottom surface is positioned at a depth between the bottom surface of the concave part and the upper surface of the substrate.
In the FETs described in these references, the thicknesses of the active layers are large at the source side beside the gate and are small at the drain side beside the gate so that the FETs have low source resistances and no deterioration in the gate drain breakdown voltage. However, because the techniques described in the references include dry etching and ion implantation which are carried out in a diagonal direction relative to the substrate surface during the formation of the recess structure, the arrangement of the source and drain electrodes with respect to the gate electrode is restricted by the diagonal direction processes, resulting in a problem. When a high power output transistor is produced by providing a plurality of transistors, the degree of freedom in the arrangement of the source and drain electrodes is severely reduced.
More particularly, in high power output transistors, source electrodes S and drain electrodes D are arranged alternatingly and gate electrodes (hereinafter referred to as gate fingers) G.sub.1 extending from a gate part G are disposed respectively between the adjacent source and drain electrodes as shown in FIG. 12(a). In the techniques described in the publications mentioned above, however, the arrangement of source and drain electrodes with respect to gate fingers is subject to restriction so that all the source and drain electrodes must be disposed at the same positions with respect to all the gate fingers; that is, each source electrode S must be disposed at the left side of a gate finger G.sub.1 and each drain electrode D must be disposed at the right side of a gate finger G.sub.1 as shown in FIG. 12(b), resulting in a problem that the arrangement of the source and drain electrodes is thus restricted. Moreover, this arrangement of the source and drain electrodes increases the degree of extension of the FET in the transverse direction, resulting in a possibility of deterioration in the FET characteristics.
In the prior art method of producing the two-stage recess structure, since the gate electrode is formed by evaporation and lift-off, as described in the respective publications, a refractory metal cannot be used as a gate material with the result that an FET having high reliability is not obtained. The reason for this is that the refractory metal melts at a high temperature and the high temperature of the refractory metal material in the evaporation process damages the photoresist used for lift-off.